1. Field of the Invention
The present invention relates to an industrial controller, and addressees in particular to a fault-tolerant technique for numeric data to be processed by operation.
2. Description of the Related Art
For control in a social infrastructure, industrial controllers in use are mostly employed for a 24-hour service as a given. Such industrial controllers are employed in those systems requiring operation processes to be error-free during their services. There is thus growing role of a fault-tolerant system allowing normal processes to be continued as a whole, even with a trouble caused in part.
Such the background is based on for development of a code theory (non-patent document 1), as well as for introduction of a fault-tolerant technique using an error correcting code, primarily in a storage system, such as a memory as a main (patent document 1). Referred now as the non-patent document 1 is “Sanzyutsu Fugou Riron (arithmetic code theory) by Akio Fukuhara and Munehiro Gotoh, Corona Ltd., Japan, April 1978, pp 32-72, pp 97-181”, and the patent document 1 is Japanese Patent Publication No. 2,665,113.
For the storage system, implementation of a fault-tolerant technique is unavoidable because of, among others, (1) the number of elements very greater than operation circuitry, and (2) the factor of availability higher than operation circuitry. Referred now as operation circuitry is circuitry composed of operation circuits for arithmetic operations, such as addition and subtraction as well as multiplication and division, and their control circuits.
On the contrary, for operation circuitry, implementing a fault-tolerant technique has not been deemed so important, for reasons such as (1) a smaller element number, (2) a lower availability factor, and (3) a greater implementation cost than the storage system.
In the field of a semiconductor process technique, however, as replies to demands for higher densification and higher speeds, recent years have observed developments of a finer fabrication of logic circuit, accompanied by an increasing difficulty in designing a robust circuit with a sufficient margin ensured as in the past.
This induces a software error due to fine particles in logic circuit.
Really, such a development of finer fabrication of circuit is accompanied by an increasing probability in occurrence of a software error due to fine particles, even in operation circuitry of an industrial controller or the like.
On the other hand, for those systems to be provided with a higher reliability as necessary to meet demands for an increase in operation speed and an increase in amount to be processed by operation, attempts are positively made for parallelization of operation circuitry.
In this respect, recently known is an operation processor provided with a plurality of operators for logic operations to be performed as desirable to one or more input operands, and configured to separate from the system such an operator as high of defective fraction, causing another operator to re-execute an operation process having been assigned to that operator, allowing even for an ensured security without damages to functions of the system (patent document 2). Referred now as the patent document 2 is Japanese Patent Application Laying-Open Publication No. 2006-228,121.